Instruction Set Architectures

ISA specifies syntax of assembly language on architectures.

An Instruction Set Architecture (ISA) defines the language and rules for a computer's processor, covering both syntax and meaning. It is a fundamental part built in the core design of a processor, influencing how instructions are executed and their complexity.

The main components that distinguish ISA's and assembly languages:

Instructions

The instruction to be processed in the opcode operand_list format.

Registers

Used to store operands, addresses, or instructions temporarily.

Memory addresses

The address in which data or instructions are stored. May point to memory or registers.

Data Types

The type of stored data.

Complex Instruction Set Computer or CISC

Used in Intel and AMD processors (most systems)

Reduced Instruction Set Computer or RISC

Used in ARM and Apple processors (smartphones/laptops)

CISC

Complex Instruction Set Computer or CISC runs more complex instructions to be run at a time which reduces overall number of instructions. Adding 2 registers would be doen in a single Instruction cycle (Fetch-Decode-Execute-Store).

RISC

Reduced Instruction Set Computer or RISC runs by splittings instructions into minor instuctions as the CPU is designed to handle simple instructions. An instruction "add r1, r2, r3" and to execute this, the processor must fetch the values from registers r2 and r3, add them, and then store the result in register r1. Each of these steps (fetch, decode, execute, store) requires a complete instruction cycle.

Some key difference

	CISC	RISC
Complexity	Favors complex instructions	Favors simple instructions
Length of instructions	Multiples of 8-bits'	Fixed length '32-bit/64-bit'
Optimization	Hardware optimized in CPU	Software optimization (in Assembly)
Example	Intel, ADM	ARM, Apple
Power consumption	High	Very low